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Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
DESCRIPTION
The MH4V36AM is an 4M word by 36-bit dynamic RAM module and consists of 2 industry standard 4M X 16 dynamic RAMs in TSOP and 1 industry standard 4M X 4(4CAS) dynamic RAMs in TSOP. The ICs are mounted on both sides of one small ceracom PC board with flash gold plating and form a convenient 68-pin package.
PIN CONFIGURATION ( TOP VIEW )
FEATURES
Type name Address OE RAS CAS Cycle access access access access time time time time time (max.ns) (max.ns) (max.ns) (max.ns) (min.ns)
MH4V36AM-6 MH4V36AM-7
60 70
15 20
30 35
15 20
110 130
Utilizes industry standard 4M X 16 DRAMs in TSOP package and industry standard 4M X 4(4CAS) DRAM in TSOP package Single 3.3V +/- 0.3V supply Low stand-by power dissipation 5.4mW (Max) . . . . . . . . . . . . . . . . . CMOS lnput level Low operating power dissipation MH4V36AM - 6 . . . . . . . . . . . . . . . . 1.155W (Max) MH4V36AM - 7 . . . . . . . . . . . . . . . . 1.100W (Max) All inputs, output TTL compatible and low capacitance 4096 refresh cycles every 64ms (A0 ~ A11) Includes 2pcs 0.22uF decoupling capacitors
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT
DQ1 1 DQ2 2 DQ3 3 DQ4 4 DQ5 5 Vss 6 DQ6 7 DQ7 8 DQ8 9 DQP1 10 DQ9 11 Vcc 12 DQ10 13 DQ11 14 DQ12 15 DQ13 16 DQ14 17 Vss 18 DQ15 19 DQ16 20 DQP2 21 Vcc 22 /CAS0 23 /CAS3 24 A0 25 A1 26 A2 27 Vss 28 A3 29 A4 30 A5 31 /RAS 32 A6 33 Vcc 34
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
DQP4 DQ32 DQ31 DQ30 DQ29 Vss DQ28 DQ27 DQ26 DQ25 DQP3 Vcc DQ24 DQ23 DQ22 DQ21 DQ20 Vss DQ19 DQ18 DQ17 Vcc /CAS2 /CAS1 /W /OE RFU(NC) Vss A11 A10 A9 A8 A7 Vcc
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Sep./19 /1996
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM FUNCTION
The MH4V36AM provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., fast page mode, CAS before RAS refresh, and delayed-write. The input conditionsfor each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs Operation RAS Read Write Read-modify-write RAS-only refresh Hidden refresh CAS before RAS refresh Standby ACT ACT ACT ACT ACT ACT NAC CAS ACT ACT ACT NAC ACT ACT DNC W NAC ACT ACT DNC DNC NAC DNC OE ACT NAC ACT DNC ACT DNC DNC Input OPN VLD VLD DNC OPN DNC DNC Output VLD OPN VLD OPN VLD OPN OPN Input/Output
Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid,APD : applied, OPN : open
BLOCK DIAGRAM
Add /W /OE /CAS3 /CAS2 /CAS1 /CAS0 /RAS
25,26,27,29,30,31,33,36,37,38,39,40
44 43 24 46 45 23 32
/RAS /UCAS
/LCAS
/OE
/W Add
/RAS
/UCAS
/LCAS
/OE
/W Add
/RAS /CAS1
/CAS3 /OE /CAS2 /CAS4 DQ2 DQ3 DQ4
/W
Add
M5M465160A
M5M465160A
M5M4V17500B
DQ1 68 58 21 10
DQP4 DQP3 DQP2 DQP1 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24
11 13 14 15 16 17 19 20 48 49 50 52 53 54 55 56 12 22 34 35 47 57
01 02 03 04 05 07 08 09
C1 to C2 0.22 uF
59 60 61 62 64 65 66 67
6
18 28 41 51 63
Vcc
Vss
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Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM ABSOLUTE MAXIMUM RATINGS
Symbol Vcc VI V0 I0 Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Output current Power dissipation Operating temperature Storage temperature Conditions With respect to Vss Ratings -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6 50 3 0 ~ 70 -40 ~ 100 Unit V V V mA W C C
Ta=25C
RECOMMENDED OPERATING CONDITIONS
Symbol Vcc Vss VIH VIL Parameter Supply voltage Supply voltage High-level input voltage, all inputs Low-level input voltage, all inputs
(Ta=0 ~70 C
, unless otherwise noted) (Note 1)
Min 3.0 0 3.0 -0.3
Limits Nom 3.3 0
Max 3.6 0 3.6 0.8
Unit V V V V
Note 1 : All voltage values are with respect to Vss
ELECTRICAL CHARACTERISTICS
Symbol VOH VOL IOZ II Parameter
(Ta=0 ~70 C, Vcc=3.3V+/- 0.3V, Vss=0V, unless otherwise noted) (Note 2)
Test conditions IOH=-2.0mA IOL=2.0mA Q floating 0V VOUT 3.6V
0V VIN 3.6V, Other inputs pins = 0V
High-level output voltage Low-level output voltage Off-state output current Input current Average supply current ICC1 (AV) from Vcc operating (Note 3,4,5) ICC2
Min 2.4 0 -10 -30
Limits Typ Max Vcc 0.4 10 30 380
Unit V V A A mA
-6 -7
RAS, CAS cycling tRC=tWC=min. output open RAS= CAS =VIH, output open RAS= CASVcc -0.2V, output open RAS=VIL, CAS cycling tPC=min. output open CAS before RAS refresh cycling tRC=min. , W Vcc - 0.2 output open
305 4 1.4 260 mA 240 380 mA 365 mA
Supply current from Vcc , stand-by Average supply current from Vcc Fast-Page-Mode (Note 3,4,5) Average supply current from Vcc CAS before RAS refresh (Note 3,5) mode -6 -7 -6 -7
ICC4(AV)
ICC6(AV)
Note 2: Current flowing into an IC is positive, out is negative. 3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column Address can be channged once or less while RAS=VIL and CAS=VIH
CAPACITANCE
Symbol CI (A)
(Ta=0~70C , Vcc=3.3V+/-0.3V, Vss=0V, unless otherwise noted)
Parameter
Test conditions
Min
Limits Typ
Max 30
Unit pF pF pF pF pF pF
Input capacitance, address inputs CI (OE) Input capacitance, OE input CI (W) Input capacitance, write control input CI (RAS) Input capacitance, RAS input CI (CAS) Input capacitance, CAS input CI / O Input/Output capacitance, data ports MIT-DS-0071-0.1
VI=Vss f=1MHZ Vi=25mVrms
36 36 36 30 25
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Preliminary Spec.
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MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM SWITCHING CHARACTERISTICS
Symbol tCAC tRAC tAA tCPA tOEA tCLZ tOFF tOEZ Access time from CAS Access time from RAS Columu address access time Access time from CAS precharge Access time from OE Output disable time after CAS high Output disable time after OE high (Ta=0~70C , Vcc=3.3V +/-0.3V, Vss=0V, unless otherwise noted , see notes 6,13,14) Limits Parameter Min (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) 5 0 0 15 15 (Note 12) (Note 12) -6 Max 15 60 30 35 15 5 0 0 15 15 Min -7 Max 20 70 35 40 20 ns ns ns ns ns ns ns ns Unit
Output low impedance time from CAS low (Note 7)
Note 6: An initial pause of 500 s is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-Only refresh or CAS before RAS refresh). Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods (greater than 64 ms) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA)/VOL=0.4V(IOL=2mA) load 100pF. The reference levels for measuring of output signal are 2.0V(VOH) and 0.8V(VOL). 8: Assumes that tRCD tRCD(max) and tASC tASC(max). 9: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD tRAD(max) and tASC tASC(max). 11: Assumes that tCP tCP(max) and tASC tASC(max). 12: tOFF(max) and tOEZ (max) defines the time at which the output achieves the high impedance state (IOUT I +/- 10 AI) and is not reference to VOH(min) or VOL(max).
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0 ~ 70 C, Vcc=3.3V +/- 0.3V, Vss=0V, unless otherwise noted See notes 13,14) Limits Symbol tREF tRP tRCD tCRP tRPC tCPN tRAD tASR tASC tRAH tCAH tDZC tDZO tCDD tODD tT Refresh cycle time RAS high pulse width Delay time, RAS low to CAS low Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width
Column address delay time from RAS low
Parameter Min 40 (Note15) 20 10 0 10 (Note16) (Note17) 15 0 0 10 15 0 0 15 15 1
-6 Max 64 50 45 20 10 0 10 30 10 15 0 0 10 15 0 0 15 15 50 1 Min
-7 Max 64 50
Unit ms ns ns ns ns ns 35 10 ns ns ns ns ns ns ns ns ns 50 ns
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low Column address hold time after CAS low (Note18) Delay time, data to CAS low Delay time, data to OE low Delay time, CAS high to data Delay time, OE high to data Transition time (Note18) (Note19) (Note19) (Note20)
Note 13: The timing requirements are assumed tT =5ns. 14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals. 15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) =tRAH(min) +2tH+tASC(min). 16: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA. 17: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC. 18: Either tDZC or tDZO must be satisfied. 19: Either tCDD or tODD must be satisfied. 20: tT is measured between VIH(min) and VIL(max).
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Preliminary Spec.
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MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
Read and Refresh Cycles
Limits Symbol tRC tRAS tCAS tCSH tRSH tRCS tRCH tRRH tRAL tOCH tORH Read cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read Setup time after CAS high Read hold time after CAS low Read hold time after RAS low Column address to RAS hold time CAS hold time after OE low RAS hold time after OE low (Note 21) (Note 21) Parameter Min 110 60 15 60 15 0 0 10 30 15 15 10000 10000 -6 Max Min 130 70 20 70 20 0 0 10 35 20 20 10000 10000 -7 Max ns ns ns ns ns ns ns ns ns ns ns Unit
Note 21: Either tRCH or tRRH must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
Limits Symbol tWC tRAS tCAS tCSH tRSH tWCS tWCH tCWL tRWL tWP tDS tDH tOEH Write cycle time RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Write setup time before CAS low Write hold time after CAS low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before CAS low or W low Data hold time after CAS low or W low OE hold time after W low (Note 23) Parameter Min 110 60 15 60 15 0 10 15 15 10 0 10 15 10000 10000 -6 Max Min 130 70 20 70 20 0 10 20 20 10 0 15 20 10000 10000 -7 Max ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
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Preliminary Spec.
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MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
Read-Write and Read-Modify-Write Cycles
Limits Symbol tRWC tRAS tCAS tCSH tRSH tRCS tCWD tRWD tAWD tCWL tRWL tWP tDS tDH tOEH Parameter Min Read write/read modify write cycle time (Note22) RAS low pulse width CAS low pulse width CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low CAS hold time after W low RAS hold time after W low Write pulse width Data setup time before W low AU Data hold time after W low AO OE hold time after W low AU AO (Note23) (Note23) (Note23) 155 105 60 105 60 0 40 85 55 15 15 10 0 10 15 10000 10000 -6 Max Min 180 120 70 120 70 0 45 95 60 20 20 10 0 15 15 10000 10000 -7 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+5tT. 23: tWCS, tCWD,tRWD and tAWD and,tCPWD are specified as reference points only. If tWCStWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWDtCWD(min), tRWDtRWD (min), tAWDtAWD(min) and tCPWDtCPWD(min) (for fast page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH ) is indeterminate.
Fast-Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle)
Limits Symbol tPC tPRWC tRAS tCP tCPRH tCPWD Parameter Min Fast page mode read/write cycle time
Fast page mode read write/read modify write cycle time
(Note 24)
-6 Max Min 45 95 125000 15 115 10 40 65 40 85 100 10 35 (Note23) 60
-7 Max
Unit ns ns 125000 15 ns ns ns ns
RAS low pulse width for read write cycle (Note25) CAS high pulse width RAS hold time after CAS precharge Delay time, CAS precharge to W low (Note26)
Note 24: All previously specified timing requirements and switching characteristics are applicable to their respective fast page mode cycle. 25: tRAS(min) is specified as two cycles of CAS input are performed. 26: tCP(max) is specified as a reference point only.
CAS before RAS Refresh Cycle
Symbol tCSR tCHR tRSR tRHR Parameter
(Note 27) Limits -6 Min Max Min 10 15 10 15 10 10 10 10 -7 Max ns ns ns ns Unit
CAS setup time before RAS low CAS hold time after RAS low Read setup time before RAS low Read hold time after RAS low
Note 27: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.
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Preliminary Spec.
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MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
Timing Diagrams Read Cycle
(Note 28)
tRC tRAS VIH VIL tCSH tCRP VIH VIL tASR VIH A0 ~ A11 VIL tRRH tRCS W VIH VIL tDZC VIH Hi-Z VIL tCAC tAA tCLZ VOH DQ (OUTPUTS) VOL Hi-Z tRAC tDZO VIH VIL tORH tOEA tOCH tOFF tCDD tRCH tRAD tRAH tASC tCAH
COLUMN ADDRESS
tRP
RAS
tRCD
tRSH tCAS
tRPC
tCRP
CAS
tRAL tCPN
tASR
ROW ADDRESS
ROW ADDRESS
DQ (INPUTS)
DATA VALID
Hi-Z
tOEZ tODD
OE
Note 28
Indicates the don't care input. VIH(min)VINVIH(max) or VIL(min)VINVIL(max) Indicates the invalid output. Indicates the skew of the four inputs.
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Preliminary Spec.
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MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
Write Cycle (Early write)
tWC tRAS VIH VIL tCSH tCRP VIH VIL tASR VIH A0 ~ A11 VIL tASR tRAH tASC tCAH
COLUMN ADDRESS ROW ADDRESS
tRP
RAS
tRCD
tRSH tCAS
tRPC tCRP
CAS
ROW ADDRESS
tWCS W VIH VIL tDS VIH VIL
tWCH
tDH
DQ (INPUTS)
DATA VALID
VOH DQ (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
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Preliminary Spec.
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MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
Write Cycle (Delayed write)
tWC tRAS VIH VIL tCSH tCRP VIH VIL tASR tRAH tASC tCAH tASR
COLUMN ADDRESS ROW ADDRESS
tRP
RAS
tRCD
tRSH tCAS
tRPC tCRP
CAS
VIH A0 ~ A11 VIL
ROW ADDRESS
tCWL tRCS W VIH VIL tWCH tDZC DQ (INPUTS) VIH VIL tCLZ Hi-Z tDS tDH
DATA VALID
tRWL tWP
VOH DQ (OUTPUTS) VOL
Hi-Z tOEZ tODD tOEH
Hi-Z
tDZO
OE
VIH VIL
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Preliminary Spec.
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MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
Read-Write, Read-Modify-Write Cycle
tRWC tRAS VIH VIL tCSH tCRP CAS VIH VIL tASR tRAH tRAD tASC tCAH tASR tRCD tRSH tCAS tRPC tCRP tRP
RAS
VIH A0 ~ A11 VIL
ROW ADDRESS
COLUMN ADDRESS
ROW ADDRESS
tRCS VIH VIL
tAWD tCWD tRWD
tCWL tRWL tWP
W
tDS tDZC DQ (INPUTS) VIH VIL tCAC tAA tCLZ VOH DQ (OUTPUTS) VOL Hi-Z tRAC tDZO VIH VIL tOEA
DATA VALID
tDH
Hi-Z
DATA VALID
Hi-Z tODD tOEZ tOEH
OE
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Preliminary Spec.
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MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
RAS-only Refresh Cycle
tRC tRAS RAS VIH VIL tRPC tCRP VIH CAS VIL tASR tRAH tASR tCRP tRP
VIH A0 ~ A11 VIL
ROW ADDRESS
ROW ADDRESS
W
VIH VIL
DQ (INPUTS)
VIH VIL
VOH DQ (OUTPUTS) VOL
Hi-Z
OE
VIH VIL
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Preliminary Spec.
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MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
CAS before RAS Refresh Cycle
tRC tRP RAS VIH VIL tCSR tRAS tRAS
tRC tRP
tRPC CAS VIH VIL
tCHR
tRPC
tCSR
tCHR
tRPC
tCRP
tCPN tASR VIH A0 ~ A11 VIL tRCH tRSR VIH W VIL tRHR tRSR tRHR
ROW ADDRESS COLUMN ADDRESS
tRCS
tCDD DQ (INPUTS) VIH VIL tOFF DQ (OUTPUTS) VOL VOH tODD tOEZ VIH OE VIL Hi-Z
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Preliminary Spec.
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MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
Hidden Refresh Cycle (Read)
(Note 29)
tRC tRAS RAS VIH VIL tCRP VIH CAS VIL tRAD tASR VIH A0 ~ A11 VIL tRCS tRAL VIH VIL tDZC tRRH tRAH
ROW ADDRESS
tRC tRP tRAS tRP
tRCD
tRSH
tCHR
tASC
tCAH
COLUMN ADDRESS
tASR
ROW ADDRESS
W
tCDD
DQ (INPUTS)
VIH Hi-Z VIL tCAC tAA tCLZ Hi-Z tRAC tDZO VIL
DATA VALID
tOFF
VOH DQ (OUTPUTS) VOL
Hi-Z tOEZ
tOEA tORH
tODD
OE
VIH
Note 29: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above.
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Preliminary Spec.
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MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
Fast Page Mode Read Cycle
tRAS VIH VIL tCSH tCRP VIH VIL tRAD tASR VIH VIL tRAL tRCS VIH VIL tDZC tDZC tDZC tRCH tRCS tRCH tRCS tRAH tASC tCAH
COLUMN-1
tRP
RAS
tPC tCAS tCP tCAS tCP
tRCD
tRSH tCAS
CAS
tCPRH tASC tCAH tASC tCAH tASR
ROW ADDRESS
A0 ~ A11
ROW ADDRESS
COLUMN-2
COLUMN-3
tRRH tRCH
W
tCDD
DQ (INPUTS)
VIH VIL Hi-Z tCAC tAA tCLZ tOFF
DATA VALID-1
Hi-Z tCAC tAA tCLZ tOFF
tCAC tAA tCLZ tOFF
VOH DQ (OUTPUTS) VOL
Hi-Z tRAC tDZO
DATA VALID-2
DATA VALID-3
tCPA tOEA tOCH tOEZ tOEA tOCH
tCPA tOEZ tOEA tOCH tOEZ
VIL OE VIH tDZO tODD tODD tDZO tORH tODD
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Preliminary Spec.
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MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
Fast Page Mode Write Cycle (Early Write)
tRAS VIH VIL tCSH tCRP VIH VIL tASR tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tCP tPC tCAS tCP tRSH tCAS
tRP
RAS
CAS
tASR
ROW ADDRESS
VIH A0 ~ A11 VIL
ROW ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
tWCS W VIH VIL tDS DQ (INPUTS) VIH VIL
tWCH
tWCS
tWCH
tWCS
tWCH
tDH
DATA VALID-1
tDS
tDH
tDS
tDH
DATA VALID-3
DATA VALID-2
VOH DQ (OUTPUTS) VOL
Hi-Z
VIH OE VIL
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Preliminary Spec.
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MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
Fast-Page Mode Write Cycle (Delayed Write)
tRAS VIH VIL tCSH tCRP VIH VIL tASR tRAH tASC tCAH tASC tCAH tRWL tCWL tRCD tCAS tCP CAS tRSH tPC tCAS
tRP
RAS
tASR
ROW ADDRESS
A0 ~ A11
VIH VIL
ROW ADDRESS
COLUMN-1
COLUMN-2
tRCS VIH VIL tWCH tDZC DQ (INPUTS) VIH Hi-Z VIL tDS
tCWL tWP
tRCS tWP
W
tWCH tDH
DATA VALID-1
tDZC tDS Hi-Z
tDH
DATA VALID-2
tCLZ DQ (OUTPUTS) VOH Hi-Z VOL tDZO VIH OE VIL tOEZ tODD tDZO Hi-Z
tCLZ Hi-Z tOEZ tODD tOEH
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( 16 / 18 )
Sep./19 /1996
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
Fast Page Mode Read-Write,Read-Modify-Write Cycle
tRAS VIH VIL tCSH tCRP VIH VIL tASR tRAD tRAH tASC tCAH tASC tCAH tCWL tRCD tCAS tCP CAS tPRWC tCAS
tRP
RAS
tRWL
tASR
ROW ADDRESS
VIH A0 ~ A11 VIL
ROW ADDRESS
COLUMN-1
COLUMN-2
tAWD tRCS VIH VIL tRWD tDZC DQ (INPUTS) VIH VIL Hi-Z tCAC tAA tCLZ DQ (OUTPUTS) VOL VOH Hi-Z tRAC tDZO VIH OE VIL tOEA
DATA VALID-1
tAWD tCWL tWP tRCS tCWD tWP
tCWD
W
tCPWD tDS tDH
DATA VALID-1
tDZC tDS Hi-Z tCAC tAA tCLZ
tDH
DATA VALID-2
Hi-Z tODD tOEZ tDZO tOEA tCPA
DATA VALID-1
Hi-Z tODD tOEZ tOEH
MIT-DS-0071-0.1
MITSUBISHI ELECTRIC
( 17 / 18 )
Sep./19 /1996
Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
MH4V36AM OUTLINE
No mounted area 11mm x 11mm
58 29 10.5 68
11mm
3.5MAX
35 24
21
A
11mm
1 12.5
1 33 x 1 = 33
34
0.5
1
1
1.2
:0~5
1.0 1.5 2.55
Detail A
MIT-DS-0071-0.1
MITSUBISHI ELECTRIC
( 18 / 18 )
Sep./19 /1996

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